Non-Power-of-Two Integer Vector Division Vectorization & X86 Lowering in LLVM

Engineering objective

System challenge

The X86 SelectionDAG combine treated extract-only users as evidence of partial demand. For legalized non-power-of-two vector returns, every result lane can appear as scalar extracts, triggering premature scalarization even when the full vector result is needed, generating inefficient scalar instructions instead of packed vector operations.

Constraints

Working within real limits

• ✕Strict preservation of existing scalarization behavior for genuinely partial lane extraction
• ✕Handle variable-index vector extract operations without unsafe assumptions
• ✕Maintain exact compatibility with all X86 target features (SSE, AVX, AVX-512)
• ✕Update LLVM lit test suites across 6 CodeGen test files with zero regressions

Approach

How it was built

1. 01

   Tracked constant extracted lane indices within SelectionDAG demand analysis.

2. 02

   Differentiated all-lanes-demanded legalized vectors from genuine sub-vector partial demand.

3. 03

   Preserved scalarization for variable-index and partial-lane extraction paths.

4. 04

   Updated lit test checks across six affected X86 CodeGen regression suites.

Technical validation

Implementation evidence

Observable engineering evidence. Discipline: MERGED UPSTREAM

Public evidence

Review the upstream contribution

Outcome

What was delivered

• Unlocked vectorized SIMD lowering for non-power-of-two vector integer division when all lanes are demanded

• Eliminated unnecessary scalar spill and register churn in generated machine code

• Merged upstream into llvm/llvm-project (merge commit d7f1904)

Technologies

Stack and tools

Previous and Next Engineering Systems